1. Technical Field
The present disclosure relates to a flat panel display with a narrow bezel structure. In particular, the present disclosure relates to a narrow bezel flat panel display in which the area for sealing material (or “sealant”) is minimized by enhancing the attaching/adhering force of the sealant disposed between the upper substrate and the lower substrate.
2. Discussion of the Related Art
A liquid crystal display device (LCD) represents video data by controlling the light transitivity of the liquid crystal layer using electric fields. According to the direction of the electric field, the LCD can be classified in two major types: one is a vertical electric field type and the other is a horizontal electric field type.
For the vertical electric field type LCD, a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate face each other for forming an electric field perpendicular to the substrate face. A twisted nematic (TN) liquid crystal layer disposed between the upper substrate and the lower substrate is driven by the vertical electric field. The vertical electric field type LCD has a higher aperture ratio than the horizontal electric field type, but it has a narrower view angle of about 90 degrees.
For the horizontal electric field type LCD, a common electrode and a pixel electrode are formed on the same substrate in parallel. A liquid crystal layer disposed between an upper substrate and a lower substrate is driven in In-Plane-Switching (IPS) mode by an electric field parallel to the substrate face. The horizontal electric field type LCD has a wider view angle of over 170 degrees and a faster response speed than the vertical electric field type LCD. However, the horizontal electric field type LCD may have a lower aperture ratio and transitivity ratio of the back light because there is no electric field over the electrodes, so that the liquid crystals disposed over the electrodes are not driven.
For most liquid crystal displays, after surface joining the thin film transistor substrate having a plurality of thin film transistors disposed in a matrix manner and the color filter substrate having a plurality of color filters, the liquid crystal layer is inserted between these surface joined substrates. Each of the pixel areas defined in the thin film transistor substrate and each of the pixel areas defined in the color filter substrate are correspondingly aligned to each other, as these two substrates are joined. In order to reduce the aligning margin in the joining process, in some cases, the color filters may be formed on the thin film transistor substrate.
FIG. 1 is a plane view illustrating the structure of a flat panel liquid crystal display according to related art. FIG. 2 is a cross-sectional view illustrating the structure of the liquid crystal display of FIG. 1 by cutting along the line I-I′ according to the related art.
With reference to FIGS. 1 and 2, the horizontal electric field type liquid crystal display in which the color filters are formed on the thin film transistor substrate includes a lower panel LP on which are disposed a plurality of pixel areas, each having one thin film transistor and one color filter in a matrix manner, an upper panel UP on which a plurality of black column spacers are disposed between the pixel areas, and a liquid crystal layer LC inserted between the lower panel LP and the upper panel UP.
The lower panel includes a lower substrate SL made of a transparent material such as the glasses. The lower substrate SL has a display area AA occupying at least most of the middle portions for representing the video data, and a non-display area NA surrounding the display area AA. The non-display area may also be referred to as the bezel area BZ. In the display area AA, a plurality of the pixel areas are disposed in a matrix manner. A thin film transistor T, a pixel electrode PXL connected to the thin film transistor T, and a color filter CF representing color are allocated in each pixel area.
In detail, the thin film transistor T is disposed at one corner of the pixel area defined in a matrix manner on the lower substrate SL. A first passivation layer PAS is deposited on the thin film transistor T for protecting it. On the first passivation layer PAS, the color filter CF is formed to cover at least most of the pixel area. For example, a red color filter CFR, a green color filter CFG, and a blue color filter CFB may be alternatively disposed on three pixel areas disposed in a serial manner. FIG. 2 shows the red and green color filters as examples with the (R) and (G) labels indicated.
A second passivation layer PAC is deposited on the color filter CF. The pixel electrode PXL connecting to the thin film transistor T is formed within the pixel area on the second passivation layer PAC. For the horizontal electric field type liquid crystal display, the pixel electrode PXL has a comb structure with a plurality of segments arrayed in parallel. Further, a common electrode COM formed as having a plurality of segments is disposed in parallel with the segments of the pixel electrode PXL one-by-one.
In addition, the upper panel UP includes an upper substrate SU made of a transparent material, such as glass. The display area AA and the non-display area NA are defined on one surface of the upper substrate SU, similarly to the lower substrate SL. A black column spacer BCS is formed on the whole area of the non-display area NA. Further, the black column spacers BCS may be disposed in the display area AA at the area corresponding to the border area between the pixel areas defined on the lower substrate SL. Usually, the black column spacers BCS are disposed between the color filters CF.
A gate driver element GIP may be formed in the non-display area NA of the lower panel LP for driving the display element formed in the display area AA. Furthermore, a ground line LIN may be disposed at the outside of the gate driver element GIP. The gate driver element GIP has a plurality of thin film transistors. For protecting these thin film transistors of the gate driver element GIP, the black column spacer BCS is usually formed to cover the whole area of the non-display area NA of the upper panel UP.
After that, with the liquid crystal layer LC, the surface of the upper panel UP on which the black column spacers BCS are disposed, and the surface of the lower panel on which the display elements are disposed are joined as facing each other so that the liquid crystal display is completed. The column spacer CS maintains an even cell gap between the upper substrate SU and the lower substrate SL. Further, the column spacer CS may provide the black matrix function between the color filters CF, as shown in FIG. 2.
In the case that the color filter CF is formed on the lower substrate SL with the thin film transistor T as mentioned above, the color filter CF is formed within the pixel areas defined on the lower substrate SL, such that the color filter CF can be just aligned with the pixel area. Further, on the upper panel UP, as only the black column spacer BCS and/or the column spacer CS are formed, the manufacturing process for the upper panel UP may be simplified.
For example, in order to join the upper panel UP and the lower panel LP, a sealing material SEAL may be disposed along the circumference along the non-display area NA of the lower panel LP. Further, the liquid crystal layer LC may be disposed within the display area AA of the lower panel LP. After that, the upper panel UP is aligned over the lower panel LP, and then is attached to the lower panel LP. The upper panel UP and the lower panel LP can be bonded to each other by the sealing material SEAL by applying an attaching force, thermal energy, and/or light energy.
For the liquid crystal display, the alignment layers are disposed on each inner upper layer of the lower panel LP and the upper panel UP. A lower alignment layer LPI is disposed on the uppermost layer of the lower panel LP. An upper alignment layer UPI is disposed on the uppermost layer of the upper panel UP. The sealing material SEAL is inserted between the lower alignment layer LPI and the upper alignment layer UPI for adhering the lower panel LP and the upper panel UP.
In the case that the bezel area BZ is minimized, the area for disposing the sealing material SEAL is minimized so that the sealing material SEAL should be disposed on the alignment layers LPI and UPI. As the sealing material SEAL has a low adhesive property with respect to the alignment layers LPI and UPI, it may cause breaking at the attached portions of the liquid crystal display. In the cases that the bezel area is relatively wide, the sealing material SEAL can be disposed as being apart from the alignment layers LPI and UPI. However, for the narrow bezel structure, the sealing material SEAL should be disposed on the alignment layers LPI and UPI. Therefore, there is a desire to develop a liquid crystal display having a structure for enhancing the adhesiveness between the sealing material and the alignment layer.